Memory device
US11050014B2 · kind B2 · utility
1Cited by
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9Claims
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Assignee
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Key dates
| Filing date | Mar 18, 2015 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | May 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device contains lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode, which are formed on a substrate in a laminated manner. In the memory device, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.