Implementing process, voltage, and/or temperature-insensitive resistance in complementary metal-oxide-semiconductors using a short-duty-clock cycle
US11050416B1 · kind B1 · utility
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16Claims
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Key dates
| Filing date | Mar 3, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Mar 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Implementation of large temperature-insensitive resistance in CMOS using short-duty-clock cycle is provided herein. Operations of a method can comprise boosting a resistance level of a switched-resistor circuit to a defined resistance level. The boosting can comprise using a short-duty-cycle clock to facilitate the boosting. Also provided is a sensor system that can comprise a short-duty-cycle clock and a switched-resistor circuit. The short-duty cycle clock boosts a resistance level of the switched-resistor circuit to a defined resistance level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.