Methods, systems, and computer readable media for testing of hardened forward error correction (FEC) implementations
US11050527B1 · kind B1 · utility
1Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Jun 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
According to one method for obtaining information from a hardened forward error correction (FEC) implementation, the method occurs at a test device implemented using at least one processor and at least one memory. The method includes copying data from a data stream that is to be processed by a hardened FEC engine; delaying the copied data while the hardened FEC engine generates corresponding error corrected output using the data; comparing the copied data and the corresponding error corrected output for differences; and generating FEC related metrics based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.