Patent · US Active

Network-on-chip link size generation

US11050672B2 · kind B2 · utility

3Cited by

4References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Honnahuggi Harinath Venkata Naga Ambica Prasad · Bengaluru, IN
Anup Gangwar · Bengaluru, IN
Nitin Agarwal · Bengaluru, IN
Ravishankar Sreedharan · Bengaluru, IN

Key dates

Filing date	Jul 22, 2019
Grant date	Jun 29, 2021
Priority date	—
Expiry date	Jul 22, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06N20/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.