Memory system with multiple channel interfaces and method of operating same
US11054855B2 · kind B2 · utility
1Cited by
14References
18Claims
0Family size
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Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.