Shadow memory checking
US11055165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Feb 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.