Memory controller and method having predictive buffering of address mapping table
US11055214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.