Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
US11055462B2 · kind B2 · utility
1Cited by
2References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 24, 2016 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Sep 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments are directed to the design and manufacture of integrated circuits, and more particularly, some embodiments are directed to the electrical modeling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, some embodiments are directed to the modeling of substrate coupling effects in these circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.