Method and apparatus for a binary neural network mapping scheme utilizing a gate array architecture
US11055613B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Aug 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a plurality of bitwise multipliers, a bitwise multiplier of the plurality of bitwise multipliers to multiply a binary synapse weight value of a neural network by a binary activation state value of a neuron of the neural network. The apparatus further comprises a plurality of majority voters, a majority voter of the plurality of majority voters to receive outputs of a first group of bitwise multipliers and to generate a majority result to indicate whether a majority of outputs of the first group of bitwise multipliers are set to a first binary value or a second binary value. The apparatus also comprises a first plurality of reconfigurable connections coupled to outputs of the plurality of bitwise multipliers and inputs of the plurality of majority voters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.