Chip packaging structure
US11056411B2 · kind B2 · utility
0Cited by
23References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip packaging structure with better reliability includes a first protective layer, a redistribution layer formed on the first protective layer, at least one chip electrically connected to the redistribution layer, and an encapsulating layer covering the redistribution layer, the chip, and the side surfaces of the first protective layer. The first protective layer comprises an exposed surface and at least four side surfaces each connected to the exposed surface. A plurality of second openings is defined in the second protective layer, and a portion of the redistribution layer is exposed from the plurality of second openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.