Small pitch super junction MOSFET structure and method
US11056585B2 · kind B2 · utility
0Cited by
11References
21Claims
0Family size
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Key dates
| Filing date | Apr 22, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.