Fixed latency configurable tap digital filter
US11057021B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.