Clock divider with quadrature error correction
US11057039B1 · kind B1 · utility
2Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Oct 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/364
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.