Method and apparatus for matrix flipping error correction
US11057060B1 · kind B1 · utility
3Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2020 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Mar 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2921
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.