Integrated circuit with physical layer interface circuit
US11057073B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2020 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | May 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40215
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for use in a differential network bus node comprising: a transceiver having a first transceiver input-output terminal and a second transceiver input-output terminal; a physical layer high terminal connected to the first transceiver input-output-terminal; a physical layer low terminal connected to the second transceiver input-output terminal; and a physical layer interface circuit comprising: a first low frequency RC matching circuit and a first high frequency RC matching circuit each connected between the first transceiver input-output-terminal and a first reference terminal; and a second low frequency RC matching circuit and a second high frequency RC matching circuit each connected between the second transceiver input-output terminal and a second reference terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.