Dual-interface flash memory controller with execute-in-place cache control
US11061670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Mar 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.