Numerical representation for neural networks
US11062202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Jul 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has a respective floating-point unit enabled to optionally and/or selectively perform floating-point operations in accordance with a programmable exponent bias and/or various floating-point computation variations. In some circumstances, the programmable exponent bias and/or the floating-point computation variations enable neural network processing with improved accuracy, decreased training time, decreased inference latency, and/or increased energy efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.