Compression techniques for pixel write data
US11062507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Dec 25, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.