Semiconductor integrated circuit device
US11062765B2 · kind B2 · utility
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Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Aug 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an SRAM cell using vertical nanowire (VNW) FETs, transistors (PD1, PD2) constituting a drive transistor are placed on both sides of a transistor (PU1) in an X direction, and transistors (PD3, PD4) constituting a drive transistor are placed on both sides of a transistor (PU2) in the X direction. An access transistor (PG1) is placed on one-hand side in the X direction of the transistor (PU1), and an access transistor (PG2) is placed on the other-hand side in the X direction of the transistor (PU1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.