Three-dimensional semiconductor memory devices
US11063057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2018 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.