Semiconductor device structure having carrier-trapping layers with different grain sizes
US11063117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2017 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Apr 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.