Semiconductor structure and method for forming the same
US11063119B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 15, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Apr 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
Abstract
Disclosed are a semiconductor structure and a method for forming same. A forming method includes: forming a first inside wall in a first groove; etching an initial channel laminated layer and an initial fin after the first inside wall is formed, where the residual initial fin is used as a fin, and the residual initial channel laminated layer located on the fin is used to form a channel laminated layer, the channel laminated layer includes a composite layer and a channel layer located on the composite layer, and the composite layer includes a first inside wall and a sacrificial layer located on a sidewall of the first inside wall; forming a pseudo gate structure across the channel laminated layer after the fin is formed; forming a source-drain doping layer in channel laminated layers on two sides of the pseudo gate structure; and removing the pseudo gate structure and the sacrificial layer after the source-drain doping layer is formed, and forming a metal gate structure at positions of the pseudo gate structure and the sacrificial layer. The first inside wall provides support for the channel layer. Therefore, even though the channel layer is relatively long, the channel layer cannot…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.