Method of fabricating semiconductor devices using a two-step gap-fill process
US11063218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Jan 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.