Phased array architecture with distributed temperature compensation and integrated up/down conversion
US11063336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Apr 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q1/2283
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.