Frame decoding circuit and method for performing frame decoding
US11063596B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 7, 2021 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Jan 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frame decoding circuit implemented in an IC die includes a frame synchronizer, receiving an input clock signal and an input frame signal in serial form, to provide an output clock signal. A phase shift of the output clock signal is adjusted according to a detected code by sampling the input frame signal at a center point for every two bits and the detected code being not a correct type. The input clock signal is divided in frequency with the phase shift for providing the output clock signal. A de-serializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, a delay-locked-loop clock signal to de-serialize the input frame signal and the input data for output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.