Serial receiver equalization circuit
US11063793B1 · kind B1 · utility
3Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/01
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An equalization circuit includes a feed-forward equalization (FFE) circuit and a decision feedback equalization (DFE) circuit. The FFE circuit includes a first FFE tap, a second FFE tap coupled to the first FFE tap, and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the first FFE tap and the second FFE tap. The programmable capacitor is coupled to the input. The DFE circuit includes an input and a DFE tap. The input is coupled to the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.