Method of calibrating a clock of a chip card circuit, and associated system
US11068019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2017 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Sep 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K7/016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A calibration method for calibrating a clock of a circuit for a smart card, which includes operations for: at a first instant, storing (S310) first time data from a terminal in the clock; at a second instant, reading (S320) second time data from the clock and corresponding to the first time data incremented by the clock as a function of a first duration between the first instant and the second instant; comparing (S330) the second time data with third time data corresponding to the first time data incremented, by the terminal or by a remote server, as a function of the first duration between the first instant and the second instant; as a function of the result of the comparison, calculating (S340) first calibration data; and storing (S350) the first calibration data in the clock. The reading of the second time data may be in a contactless manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.