Timing controller based on heap sorting, modem chip including the same, and integrated circuit including the timing controller
US11068021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2018 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Mar 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modem chip includes a processor configured to generate instructions, a timing controller configured to respectively generate control signals corresponding to the instructions at the execution times of the instructions, and a plurality of intellectual property blocks, each configured to operate in response to a corresponding control signal of the control signals. The timing controller includes a heap sorting circuit configured to sort the instructions according to execution orders of the instructions based on heap sorting using the execution times, a reference counter configured to generate a reference time, and a signal generator configured to generate a control signal corresponding to a current instruction when the reference time matches the execution time of the current instruction having a highest execution order among the instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.