Vectorizing conditional min-max sequence reduction loops
US11068247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2018 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Oct 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/456
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Algorithms, examples, and related technology for automatic vectorization of a particular class of loops is described. The loops, denoted “CMMSR loops”, operate to find an extremum and also utilize an index denoting the position of the extremum in an array or other multi-element input. CMMSR loops are identified in a language translator by matching a specified template or having a specified set of parsing results, or both. Generated vectorization code includes, for example, code to compute candidates for the extremum, code to select the same instance of the extremum as a scalar execution when the input contains multiple instances, and wind-down code to compute an index expression based on the selected instance of the extremum. Vectorizations may execute on SIMD hardware or other vector processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.