Processing system, related integrated circuit, device and method
US11068255B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Mar 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07C5/008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.