Processing system, related integrated circuit and method for generating interrupt signals based on memory address
US11068331B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Oct 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.