Reducing impact of context switches through dynamic memory-mapping overallocation
US11068411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jan 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method including: receiving, via a processor, established upper bounds for dynamic structures in a multi-tenant system; creating, via the processor, arrays comprising related memory-management unit (MMU) mappings to be placed together; and placing the dynamic structures within the arrays, the placing comprising for each array: skipping an element of the array based on determining that placing a dynamic structure in that element would cause the array to become overcommitted and result in a layout where accessing all elements would impose a translation look aside buffer (TLB) replacement action; and scanning for an array-start entry by placing the start of a first element at an address from which an entire array can be placed without TLB contention, and accessing, via the processors, all non-skipped elements without incurring TLB replacements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.