Oscillation reduction unit for a bus system and method for reducing an oscillation tendency when transitioning between different bit states
US11068429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2018 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Aug 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An oscillation reduction unit for a bus system. The oscillation reduction unit has two transistors, which are situated anti-serially between a first bus wire of a bus of the bus system and a second bus wire of the bus, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and a time control block for switching the two transistors and designed to switch on the two transistors while a signal on the first and/or second bus wire and/or a transmission signal, from which the signals on the first and/or second bus wire are generated, changes from a dominant state to a recessive state, and designed to switch off the two transistors if the signal on the first and/or second bus wire and/or the transmission signal is/are switched into the recessive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.