Processing apparatus and method for artificial neuron
US11068775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2018 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | May 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing apparatus applied in an artificial neuron is disclosed. The processing apparatus comprises a parser, a lookup array, a summing circuit and a MAC circuit. The parser parses one of M packets to extract a non-zero weight value from a header of the one packet, to identify a plurality of bit positions with a specified digit from a payload of the one packet, and to output the non-zero weight value and the bit positions in parallel. The lookup array contains N synapse values and is indexed by the bit positions in parallel to generate a plurality of match values. The summing circuit sums up the match values to generate a sum value. The MAC circuit generates a product of the non-zero weight value and the sum value, and generates an accumulate value based on the product and at least one previous accumulate value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.