Memory with symmetric read current profile and read method thereof
US11069401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jun 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.