Semiconductor memory device
US11069407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Mar 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/841
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.