Method of manufacturing a semiconductor device including a plurality of channel patterns
US11069580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device manufacturing method includes forming a gate dielectric layer surrounding first semiconductor patterns and second semiconductor patterns; forming a first organic pattern covering the second semiconductor patterns; forming a sacrificial pattern interposed between the first semiconductor patterns and exposing both side surfaces of the first semiconductor patterns, and a conductive pattern surrounding the second semiconductor patterns and disposed between the first organic pattern and the second semiconductor patterns; forming a second organic pattern covering the first semiconductor patterns, the gate dielectric layer, the sacrificial pattern, and the first organic pattern; and forming a cross-linking layer interposed between the first organic material pattern and the second organic material pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.