Semiconductor wafer, bonding structure and wafer bonding method
US11069647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer, a bonding structure, and a wafer bonding method are provided. In the semiconductor wafer, a bonding pad which is electrically connected to the interconnection structure is formed in the top cover layer, and a bonding alignment mark formed by a point array is disposed in the top cover layer. In this way, the bonding alignment mark is disposed in the top cover layer, and the top cover layer is not covered by another material layer, thereby facilitating recognition of the alignment pattern by the bonding device and increasing the alignment window in bonding process. Moreover, the bonding alignment mark is formed by a point array, thereby facilitating integration of the process for forming the bonding alignment mark with the bonding hole process and avoiding defects such as the dishing phenomenon in the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.