Ultra low-voltage circuits
US11070129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Apr 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/134
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.