Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)
US11070200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2018 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.