Test circuit for a digital phase-locked loop
US11070214B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Oct 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Integrated Circuit (IC) includes a digital phase-locked loop (DPLL) circuit and DPLL Diagnostics circuitry (DPLL-DC). The DPLL circuit includes an oscillator, a digital phase detector and a digital feedback bus (DPLL-DFB). The oscillator is configured to generate an output signal. The digital phase detector is configured to generate a digital feedback signal indicative of a phase difference between the output signal and a reference input signal. The DPLL-DFB is configured to feed-back the digital feedback signal for controlling the oscillator. The DPLL-DC is coupled to the DPLL-DFB and is configured to monitor events depending at least on the digital feedback signal transferred on the DPLL-DFB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.