Method and apparatus for implementing multirate SerDes systems
US11070224B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | May 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/207
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.