Physical hardware clock chaining
US11070304B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Feb 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0673
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.