Low pin count reversible scan architecture
US11073556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2020 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Apr 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.