Patent · US Active

Methods and apparatus for boot time reduction in a processor and programmable logic device environment

US11074085B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Yah Wen Ho · Bukit Mertajam, MY
Vincent J. Zimmer · Federal Way, US
Tung Lun Loo · Bukit Mertajam, MY

Key dates

Filing date	Sep 26, 2017
Grant date	Jul 27, 2021
Priority date	—
Expiry date	Sep 26, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2213/0026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.