Switch timing controlling circuit, switch timing controlling method and display device
US11074847B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 31, 2020 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Jul 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2380/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A switch timing controlling circuit includes a first timing controlling circuit including a first inverting sub-circuit configured to form a first inverting signal that is inverted from an initial signal having a first level as an inactive level and a second level as an active level input from an initial signal terminal; a first delaying sub-circuit configured to delay a time point of the first inverting signal at which the first inverting signal changes from the first level to the second level to form a first delaying signal; and a second inverting sub-circuit configured to form a reset signal inverted from the first delaying signal; and a second timing controlling circuit including a second delaying sub-circuit configured to delay a time point of the initial signal at which the initial signal changes from the first level to the second level to form a display control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.