Semiconductor circuit and semiconductor circuit system
US11074972B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2018 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Dec 4, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.