Patent · US Active

Si-passivated GE gate stack

US11075083B2 · kind B2 · utility

0Cited by

6References

20Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Hiroaki Arimura · Leuven, BE
Antony Premkumar Peter · Heverlee, BE
Hendrik F.W. Dekkers · Tienen, BE

Key dates

Filing date	Nov 22, 2019
Grant date	Jul 27, 2021
Priority date	—
Expiry date	Nov 22, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/685
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (100). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200° C., and a plasma power less than or equal to 100 W.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.