Microelectronics package with ultra-low-K dielectric region between stacked antenna elements
US11075453B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2020 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Feb 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q21/064
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.