Patent · US Active

System and method for calibrating digital phase locked loop

US11075638B1 · kind B1 · utility

3Cited by

6References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Anand Kumar Sinha · Noida, IN
Krishna Thakur · Nagar, IN
Pawan Sabharwal · Ghaziabad, IN

Key dates

Filing date	Dec 28, 2020
Grant date	Jul 27, 2021
Priority date	—
Expiry date	Dec 28, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A calibration system of a digital phase locked loop (DPLL) includes a calibration circuit and a digitally controlled oscillator (DCO). The calibration circuit is configured to receive an input signal and a feedback signal, and generate a digital signal, based on a frequency of the input signal, a frequency of the feedback signal, and an input bias code. The DCO is configured to receive the input bias code and the digital signal, and generate a bias signal based on the input bias code. The DCO is further configured to generate an analog signal based on the bias signal and the digital signal, and generate the feedback signal such that the frequency of the feedback signal is based on an amplitude of the analog signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.